Continued CMOS scaling requires geometrical scaling of device dimensions with every technology generation. This primarily includes scaling the device width and length as well as other features of the technology. At short device widths, the formation and behavior of the active regions are dominated by the surrounding isolations regions. For example, the presence of high stress fields used in modern strained silicon technologies modulates the diffusion of dopants near the isolation regions. These differences, for instance, manifest as a change in device electrostatics (for example, threshold voltage of the device). Consequently, devices fabricated at various device widths are electrically different. This creates huge technological problems, as a typical technology includes devices drawn at a range of device widths. Such differences can easily derail a given technology from full entitlement. Hence, for continued CMOS scaling, devices fabricated at smaller widths are expected to perform similar to larger width devices. In other words, the technology is expected to demonstrate a uniform narrow width effect.
In various aspects, the present invention addresses the problem of creating devices with a uniform narrow width effect.